Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
OAK 국가리포지터리 - OA 학술지 - Transactions on Electrical and Electronic Materials - High-speed CMOS Frequency Divider with Inductive Peaking Technique
Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
Figure 2 from New CML latch structure for high speed prescaler design | Semantic Scholar
Electronics | Free Full-Text | 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
High Speed Digital Blocks
Electronics | Free Full-Text | A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs
A Novel Ultra High-Speed Flip-Flop
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Analysis and Design of High-Speed CMOS Frequency Dividers
High Speed Digital Blocks
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
Schematics of latch and D flip-flop. (a) Latch. (b) D flip-flop. | Download Scientific Diagram
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
